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#include "at32f403a_407_board.h"
#include "at32f403a_407_clock.h"
int main(void)
{
system_clock_config();
/* peripheral clocks configuration */
crm_configuration();
/* gpio configuration */
gpio_configuration();
/* tmr3 time base configuration */
tmr_base_init(TMR3, 2, 0);
tmr_cnt_dir_set(TMR3, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR3, TMR_CLOCK_DIV1);
tmr_output_default_para_init(&tmr_oc_init_structure);
tmr_oc_init_structure.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
tmr_oc_init_structure.oc_idle_state = FALSE;
tmr_oc_init_structure.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_oc_init_structure.oc_output_state = TRUE;
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_1, &tmr_oc_init_structure);
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_1, 1);
/* input trigger selection */
tmr_trigger_input_select(TMR3, TMR_SUB_INPUT_SEL_IS0);
/* slave mode selection: hang mode */
tmr_sub_mode_select(TMR3, TMR_SUB_HANG_MODE);
/* tmr4 time base configuration */
tmr_base_init(TMR4, 1, 0);
tmr_cnt_dir_set(TMR4, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR4, TMR_CLOCK_DIV1);
tmr_output_default_para_init(&tmr_oc_init_structure);
tmr_oc_init_structure.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
tmr_oc_init_structure.oc_idle_state = FALSE;
tmr_oc_init_structure.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_oc_init_structure.oc_output_state = TRUE;
tmr_output_channel_config(TMR4, TMR_SELECT_CHANNEL_1, &tmr_oc_init_structure);
tmr_channel_value_set(TMR4, TMR_SELECT_CHANNEL_1, 1);
/* input trigger selection */
tmr_trigger_input_select(TMR4, TMR_SUB_INPUT_SEL_IS0);
/* slave mode selection: hang mode */
tmr_sub_mode_select(TMR4, TMR_SUB_HANG_MODE);
/* tmr1 time base configuration */
tmr_repetition_counter_set(TMR1, 4);
tmr_base_init(TMR1, 319, 0);
tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
tmr_output_default_para_init(&tmr_oc_init_structure);
tmr_oc_init_structure.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
tmr_oc_init_structure.oc_idle_state = TRUE;
tmr_oc_init_structure.occ_idle_state = FALSE;
tmr_oc_init_structure.oc_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_oc_init_structure.occ_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_oc_init_structure.oc_output_state = TRUE;
tmr_oc_init_structure.occ_output_state = TRUE;
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_oc_init_structure);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 159);
tmr_primary_mode_select(TMR1, TMR_PRIMARY_SEL_OVERFLOW);
tmr_sub_sync_mode_set(TMR1, TRUE);
tmr_output_enable(TMR1, TRUE);
/* tmr enable counter */
tmr_counter_enable(TMR1, TRUE);
tmr_counter_enable(TMR3, TRUE);
tmr_counter_enable(TMR4, TRUE);
while(1)
{
}
}
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