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#include "at32f403a_407_board.h"
#include "at32f403a_407_clock.h"
int main(void)
{
system_clock_config();
at32_board_init();
/* get system clock */
crm_clocks_freq_get(&crm_clocks_freq_struct);
/* turn led2/led3/led4 on */
at32_led_on(LED2);
at32_led_on(LED3);
at32_led_on(LED4);
/* enable tmr1/gpioa/gpiob/dma clock */
crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
/* timer1 output pin Configuration */
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
/* tmr1 configuration: generate 1 pwm signal using the dma burst mode:
the tmr1clk frequency is set to system_core_clock (hz), to get tmr1 counter
clock at 24 mhz the prescaler is computed as following:
- prescaler = (tim1clk / tmr1 counter clock) - 1
system_core_clock is set to 240 mhz .
the tmr1 period is 5.86 khz: tmr1 frequency = tmr1 counter clock/(arr + 1)
= 24 mhz / 4096 = 5.86khz khz
tmr1 channel1 duty cycle = (tim1_ccr1/ tmr1_arr)* 100 = 33.33% */
tmr_base_init(TMR1, 0xFFFF, (crm_clocks_freq_struct.sclk_freq/24000000)-1);
tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
/* channel 3 configuration in output mode */
tmr_output_default_para_init(&tmr_output_struct);
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
tmr_output_struct.oc_output_state = TRUE;
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_output_struct.oc_idle_state = TRUE;
tmr_output_struct.occ_output_state = FALSE;
tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_output_struct.occ_idle_state = FALSE;
/* channel 3 */
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 0xFFF);
/* enable tmr1 overflow dma request */
tmr_dma_request_enable(TMR1, TMR_OVERFLOW_DMA_REQUEST, TRUE);
tmr_dma_control_config(TMR1, TMR_DMA_TRANSFER_3BYTES, TMR_PR_ADDRESS);
/* dma config for tmr1 overflow dma request */
/* dma1 channel5 configuration */
dma_reset(DMA1_CHANNEL5);
dma_init_struct.buffer_size = 3;
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)src_buffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&TMR1->dmadt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = TRUE;
dma_init(DMA1_CHANNEL5, &dma_init_struct);
dma_channel_enable(DMA1_CHANNEL5, TRUE);
/* output enable */
tmr_output_enable(TMR1, TRUE);
/* enable tmr1 */
tmr_counter_enable(TMR1, TRUE);
while(1)
{
}
}
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