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#include "at32f403a_407_board.h"
#include "at32f403a_407_clock.h"
int main(void)
{
system_clock_config();
/* peripheral clocks configuration */
crm_configuration();
/* nvic configuration */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_irq_enable(TMR3_GLOBAL_IRQn, 0, 0);
/* gpio configuration */
gpio_configuration();
/* tmr3 configuration: output compare toggle mode:
tmr3clk = system_core_clock / 2,
the objective is to get tmr3 counter clock at 12 mhz:
- prescaler = (tmr3clk / tmr3 counter clock) - 1
cc1 update rate = tmr3 counter clock / ccr1_val = 366.2 hz
cc2 update rate = tmr3 counter clock / ccr2_val = 732.4 hz
cc3 update rate = tmr3 counter clock / ccr3_val = 1464.8 hz
cc4 update rate = tmr3 counter clock / ccr4_val = 2929.6 hz */
/* compute the prescaler value */
prescaler_value = (uint16_t)(system_core_clock / 24000000) - 1;
/* tmre base configuration */
tmr_base_init(TMR3, 65535, prescaler_value);
tmr_cnt_dir_set(TMR3, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR3, TMR_CLOCK_DIV1);
/* output compare toggle mode configuration: channel1 */
tmr_output_default_para_init(&tmr_oc_init_structure);
tmr_oc_init_structure.oc_mode = TMR_OUTPUT_CONTROL_SWITCH;
tmr_oc_init_structure.oc_idle_state = FALSE;
tmr_oc_init_structure.oc_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_oc_init_structure.oc_output_state = TRUE;
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_1, &tmr_oc_init_structure);
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_1, ccr1_val);
/* output compare toggle mode configuration: channel2 */
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_2, &tmr_oc_init_structure);
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_2, ccr2_val);
/* output compare toggle mode configuration: channel3 */
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_3, &tmr_oc_init_structure);
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_3, ccr3_val);
/* output compare toggle mode configuration: channel4 */
tmr_output_channel_config(TMR3, TMR_SELECT_CHANNEL_4, &tmr_oc_init_structure);
tmr_channel_value_set(TMR3, TMR_SELECT_CHANNEL_4, ccr4_val);
/* tmr enable counter */
tmr_counter_enable(TMR3, TRUE);
/* tmr it enable */
tmr_interrupt_enable(TMR3, TMR_C1_INT | TMR_C2_INT | TMR_C3_INT | TMR_C4_INT, TRUE);
while(1)
{
}
}
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