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#include "at32f403a_407_board.h"
#include "at32f403a_407_clock.h"
int main(void)
{
system_clock_config();
at32_board_init();
/* get system clock */
crm_clocks_freq_get(&crm_clocks_freq_struct);
/* turn led2/led3/led4 on */
at32_led_on(LED2);
at32_led_on(LED3);
at32_led_on(LED4);
/* enable tmr1/gpioa/gpiob clock */
crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
/* timer1 output pin configuration */
gpio_init_struct.gpio_pins = GPIO_PINS_8 | GPIO_PINS_9 | GPIO_PINS_10;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_13 | GPIO_PINS_14 | GPIO_PINS_15;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOB, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_12;
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOB, &gpio_init_struct);
/* tmr1 configuration to:
1/ generate 3 complementary pwm signals with 3 different duty cycles:
tmr1clk is fixed to system_core_clock, the tmr1 prescaler is equal to 0 so the
tmr1 counter clock used is system_core_clock.
* system_core_clock is set to 192 mhz .
the objective is to generate pwm signal at 17.57 khz:
- tmr1_period = (system_core_clock / 17570) - 1
the three duty cycles are computed as the following description:
the channel 1 duty cycle is set to 50% so channel 1n is set to 50%.
the channel 2 duty cycle is set to 25% so channel 2n is set to 75%.
the channel 3 duty cycle is set to 12.5% so channel 3n is set to 87.5%.
the timer pulse is calculated as follows:
- channelxpulse = duty_cycle * (tmr1_period - 1) / 100
2/ insert a dead time equal to 11/system_core_clock ns
3/ configure the brake feature, active at high level, and using the automatic
output enable feature
4/ use the locking parameters level1. */
/* compute the value to be set in arr regiter to generate signal frequency at 17.57 khz */
timer_period = (crm_clocks_freq_struct.sclk_freq / 17570 ) - 1;
/* compute ccr1 value to generate a duty cycle at 50% for channel 1 and 1n */
channel1_pulse = (uint16_t) (((uint32_t) 5 * (timer_period - 1)) / 10);
/* compute ccr2 value to generate a duty cycle at 25% for channel 2 and 2n */
channel2_pulse = (uint16_t) (((uint32_t) 25 * (timer_period - 1)) / 100);
/* compute ccr3 value to generate a duty cycle at 12.5% for channel 3 and 3n */
channel3_pulse = (uint16_t) (((uint32_t) 125 * (timer_period - 1)) / 1000);
tmr_base_init(TMR1, timer_period, 0);
tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
/* channel 1, 2, 3 and 4 Configuration in output mode */
tmr_output_default_para_init(&tmr_output_struct);
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
tmr_output_struct.oc_output_state = TRUE;
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_output_struct.oc_idle_state = TRUE;
tmr_output_struct.occ_output_state = TRUE;
tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_LOW;
tmr_output_struct.occ_idle_state = FALSE;
/* channel 1 */
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, channel1_pulse);
/* channel 2 */
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_2, channel2_pulse);
/* channel 3 */
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_3, channel3_pulse);
/* automatic output enable, stop, dead time and lock configuration */
tmr_brkdt_default_para_init(&tmr_brkdt_config_struct);
tmr_brkdt_config_struct.brk_enable = TRUE;
tmr_brkdt_config_struct.auto_output_enable = TRUE;
tmr_brkdt_config_struct.deadtime = 11;
tmr_brkdt_config_struct.fcsodis_state = TRUE;
tmr_brkdt_config_struct.fcsoen_state = TRUE;
tmr_brkdt_config_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_HIGH;
tmr_brkdt_config_struct.wp_level = TMR_WP_LEVEL_3;
tmr_brkdt_config(TMR1, &tmr_brkdt_config_struct);
/* output enable */
tmr_output_enable(TMR1, TRUE);
/* enable tmr1 */
tmr_counter_enable(TMR1, TRUE);
while(1)
{
}
}
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